This invention pertains generally to any network using a frequency multiplier where the multiplication ratio is programmable through a configuration register.
In an integrated circuit (IC) containing a frequency multiplier all operations and processing are typically controlled by a voltage controlled oscillator (VCO) which directly or indirectly produces an output clock signal. Changing the multiplication ratio of the frequency multiplier usually creates an unstable period for the voltage controlled oscillator which is itself part of a phase locked loop (PLL). During this period of instability, the output clock signal may vary above or below the desired frequency before finally locking onto the selected output clock frequency. Since the IC uses the output clock to control its processing functions, the processing may be corrupted during the period of clock instability. Further, the frequency multiplier output clock is used to control the configuration register in which the desired multiplication ratio is stored. If the output clock signal is disturbed the desired multiplication ratio may be lost. This condition may result in a permanently unlocked condition caused by an endless loop in which the desired change in the multiplication ratio leads to frequency instability, which leads to improper latching of the new multiplication ratio, which leads to a random change in the multiplication ratio, which leads to frequency instability, and so forth. That is, a change in the multiplication ratio leads to a condition in which the multiplication ratio is continuously altered. In addition, ideally, the frequency multiplier output clock should always be enabled without cessation or interruption by any gating or other logical function.
A clock control scheme is disclosed by Walsh et al. in U.S. Pat. No. 5,842,005 entitled CLOCK CONTROL CIRCUITS, SYSTEMS AND METHODS.
Walsh et al. utilizes a clock gate which receives a clock control signal to prevent clock pulses from reaching a central processing unit within one cycle of a change in the clock control signal. However, as described above, such gating of the clock signal is generally undesirable.
The present invention addresses the need to provide a simple and reliable method of changing the multiplication ratio of a programmable frequency multiplier. The output clock signal of the frequency multiplier is used to control circuitry used for programming of the desired multiplication ratio. Two clock domains are defined in the present invention. A first clock domain is the Reference Clock Domain which contains all of the cells or components which derive their function from the input reference clock signal of the integrated circuit. A second clock domain is the Internal Clock Domain which contains all of the cells or components which derive their function from the output clock signal of the frequency multiplier. This second clock domain includes all of the IC operation and processing blocks and therefore represents most of the components of the IC.
The Internal Clock Domain includes a Software Reset configuration register which controls changes in the multiplication ratio. In general, a change in clock frequency (induced by a change in the frequency multiplication ratio) is a critical operation at which time a reset of the internal clock domain circuits is possible. When the multiplication ratio is to be altered, the software configuration register conditions the multiplication ratio data to be latched at the control input terminal of the frequency multiplier concurrently with the generation of a software reset command to the cells within the Internal Clock Domain as synchronized by the reference clock signal. The Software Reset configuration register will, therefore, be reset concurrently with a change in the multiplication ratio. Resetting the Software Reset configuration register in this manner prevents the contents of this register from being corrupted, thereby preventing random frequency changes to the frequency multiplier during the period of instability and insures that the multiplication ratio being passed to the frequency multiplier will remain stable.